# CPS Intelligence > Semiconductor IC circuit analysis and reverse engineering. CPS stands for > Chip Position System. Founded 2008 in Zhubei City, Hsinchu County, Taiwan. CPS analyses integrated circuits: decapsulating the package, removing metal layers one at a time, capturing high-resolution die imagery, and recovering hierarchical schematics that customers can read and cross-reference against the physical layout. ## Key facts - Founded: 2008 - Customers worldwide: 891 - Reports produced to date: over 5,000 - Finest process node analysed: 3nm (more than ten devices) - Also processed: 3D NAND with more than 128 layers, SiP packages containing 10 dies - Publicly listed reports available for purchase: 748 - Manufacturers covered in the public library: 205 - Support response time: within 24 hours - Legal name: CPS Intelligence Co., Ltd (資利通設計開發股份有限公司) - Contact: info@cps-i.com, +886-3-5601131 ## Services - **IC circuit analysis** — full or partial schematic recovery from physical silicon. Delivered as a BrigenOne project file, Cadence-compatible schematics, and a hierarchical PDF report. https://www.cps-i.com/en/services/circuit-analysis/ - **IC reverse engineering** — what the process physically involves: decapsulation, delayering, layer-by-layer imaging, device identification, circuit extraction and double-extraction verification. Includes the capability limits and what the service does not cover. https://www.cps-i.com/en/services/reverse-engineering/ - **Cost and competitive analysis** — estimate a competitor's cost structure from measured die size, process node, layer count and package construction. https://www.cps-i.com/en/services/cost-analysis/ - **Partial scopes** — high-resolution layer-by-layer die imaging only, or device identification and net annotation only. ## How pricing works A common misconception is that price scales with the size of the die. In fact: - **Die imaging** is billed per shot. The shot count follows process node, the area you ask us to work on and the layer count: a finer node needs higher magnification, and the field of view shrinks with the square of it, so the same region imaged at 10,000x takes four times as many frames as at 5,000x. Note this is the outlined scope area, not the die size — partial scopes are common. - **Delayering** is billed per hour, driven by metal layer composition (aluminium or copper) and the number of metal layers — not by area, and not by process node. - **Circuit analysis** is billed per hour, driven by device count together with connectivity. At the same device count, a densely laid out analog IC has far more nets to recover than a structurally simple part. A small die can therefore cost more than a large one. Every project is evaluated individually before quotation, and the evaluation is free of charge — decapsulation, delayering and SEM time included. https://www.cps-i.com/en/pricing/ ## Licensing models - **Non-Exclusive** (default): the baseline price. CPS may later list the report publicly for other customers to buy. - **Exclusive**: three times the baseline. Never resold; held only by the commissioning party. About 40% of commissions choose this. - **Rush** is a separate option, not a third licensing model: three times the price to bypass the queue and enter the workflow at top priority. Engineering time still has a floor — a rush buys queue position, not a shorter process, and CPS does not commit to unachievable lead times. Reports from Exclusive commissions, imaging-only projects and annotation-only projects never appear in the public library. **Client confidentiality is unconditional.** Regardless of licensing model, CPS never discloses who commissioned a report, which chip they asked about, or when. This is not an upgrade tied to the Exclusive model — it applies to every customer. ## Report library 748 chips already analysed, searchable by part number, manufacturer, device type and analysis depth. Each part has its own page. - Library: https://www.cps-i.com/en/reports/ - Individual report: https://www.cps-i.com/en/reports/{part-number-slug}/ - Device types: Driver (134), Amplifier (93), Others (75), Sensor (59), Power Management (57), Regulator (44), Switch (43), DC/DC (37), Buck (28), Processor (28), RF (28), Controller (20) - Leading manufacturers: TI (194), Analog Devices (32), Maxim (27), Semtech (23), NXP (17), ON Semiconductor (15), SGMicro (14), Avago (13), Infineon (13), Skyworks (12), 3PEAK (11), Linear (11), MPS (11), Fairchild (10), ST (9) ## BrigenOne CPS's own circuit viewer, delivered with every report. Cross-references layout and schematic in both directions, traces nets across views, steps through captured metal layer imagery, supports dual-screen working, and uses Cadence key bindings. Runs on Windows without installation. https://www.cps-i.com/en/brigenone/ ## The lab Four in-house processes: decapsulation, RIE delayering, SEM die imaging with custom stitching software, and cross-section analysis. https://www.cps-i.com/en/lab/ ## CPS School CPS periodically releases past circuit analysis reports free of charge to students, professors and anyone studying semiconductor design. Reports are read online as PDFs and are not downloadable. Reading needs no permission; using a report for teaching or in a publication requires prior written consent from CPS, and must credit CPS as the source. https://www.cps-i.com/en/school/ ## Careers CPS is recruiting international agents, sales staff and contract circuit analysis engineers. Applications by email to info@cps-i.com. https://www.cps-i.com/en/careers/ ## Languages Every page exists in English (/en/) and Traditional Chinese (/zh/), linked with hreflang. English is the default. ## Full index - Sitemap: https://www.cps-i.com/sitemap.xml - FAQ: https://www.cps-i.com/en/faq/ - Contact: https://www.cps-i.com/en/contact/