Decapsulation, layer-by-layer removal, SEM imaging and hierarchical schematic recovery — all in our own lab. What you receive is not a stack of images, but data you can trace and cross-reference against the layout.
Over eighteen years, the reasons almost always fall into three.
In analog IC design, the wrong architecture is the most expensive mistake there is. Rather than cycling between simulation and tape-out, look first at how a chip that survived in the market actually solved the problem.
IC circuits are complex, and architecture and process are usually the hardest and riskiest part of development. Getting stuck there wastes engineering time and can cost you an entire product cycle.
A datasheet states the result, not the method. Which architecture a rival chose, how many metal layers, which process node — those answers only come from the physical die, and they inform both roadmap and pricing decisions.
Each step is confirmed before the next begins, so scope never drifts halfway through.
Establish what the die allows and how much of it you need.
Registration asks only for your company details and a corporate email address. Once the account is open you can raise a commission directly — with complete information the evaluation can begin without waiting for a sample to arrive, and without a round of emails to pin down requirements. Progress, quotations and deliverables then live in one place.
If you already hold the data, simply supply the process node, metal and poly layer counts, die size and a die photograph in which the device layout is clearly visible — that is enough for us to begin. Alternatively, send us an IC sample: the evaluation is free of charge, and you receive the process node, metal and poly layer counts, die size and a die photograph. Obtaining those means decapsulation, delayering and SEM time; CPS does not bill for it. Either route works — and a datasheet, if you have one, makes the subsequent quotation more accurate.
We produce an evaluation report covering die size, process node, metal and poly layer counts, and a top-layer photograph.
Mark up the top-layer photograph directly to show which regions you want imaged at high resolution or analysed.
Price, lead time and deliverables, all in writing.
A quotation built from your requirements: itemised pricing, engineering scope, deliverables list, lead time, payment terms and copyright notice. If the figure does not fit your budget, the scope can be adjusted — narrow it, or keep only the critical blocks — and we requote against the revised scope, as many times as it takes.
Issue a formal purchase order, or simply sign the LOA and settle the initial payment.
Once the PO or signed LOA arrives, we confirm the exact completion date and the final deliverables list, and ask you to ship the number of samples stated in the LOA — delayering is destructive and each layer is a single attempt, so a short count stalls everything downstream.
Once it reaches the lab, progress is visible in the Portal.
Decapsulation, delayering, layer-by-layer imaging, netlist extraction and hierarchical schematic assembly — all in house. The assembled circuits then go to contracted consultants in different specialisms around the world for an independent circuit review: the reviewer is not the person who did the work, which is the only way a blind spot in the reading gets named.
BrigenOne project, schematic files and PDF report. Follow-up questions answered within 24 hours.
Scope can be a single critical block or the whole die. If you are unsure how much you need, start with the evaluation report — that is exactly what it is for.
One analysis in three forms: BrigenOne to trace and query, Cadence files you can edit or export as a netlist, and a PDF that opens anywhere. All three are built from the same data, so any one can be used to verify the other two.
Our own circuit viewer: bidirectional cross-indexing between layout and circuit elements, cells and nets; multi-layer high-resolution die imagery; on-screen measurement. No installation required.
Schematic files compatible with Cadence Composer. Edit them in Cadence, or convert to a netlist for simulation. (Simulation is not part of this service.)
The circuit laid out by hierarchy as a PDF, readable on any platform, with die photo, device summary and architecture list.
Flattened schematics are partitioned along the physical layout — by guard ring — with the correspondence marked in both the layout and the schematic, and inter-block nets connected and correctly named. This is what makes a report readable, and it is what customers comment on most.
Scope is your decision, and cost follows scope.
Some customers only need to understand one critical block — the protection circuit in a power IC, or the sampling front end of an ADC. Analysing the full die would be wasted effort.
Others need only high-resolution layer-by-layer die imagery, or device identification and net annotation without full schematic recovery. Both are available on their own.
Marking the region directly on the top-layer photograph from the evaluation report is the clearest way to communicate scope — we quote against exactly what you circle.
Memory arrays and auto-placed-and-routed (APR) digital blocks are outside the scope of analysis. And on a partial scope, nets crossing the boundary are not traced beyond it — the schematic shows signals entering and leaving, but where they go outside the region is not part of that engagement. If a signal’s source or destination matters to you, include it in the region you outline.
The value of a circuit analysis report is its accuracy. One wrong net can cost a customer days.
Netlist extraction is performed twice and the two results compared line by line. Where necessary the die is imaged again against a different background and extracted separately — the same misreading rarely survives two independent passes.
A quality team of senior engineers reviews each low-level block as it is completed, followed by a full review once every block is done. One pass at block level, one at project level.
A low-level circuit error guide, written collaboratively by senior engineers, catalogues common faults and their fixes as part of the company knowledge base. New engineers do not have to rediscover the same traps.
An internal issue-tracking process ties every error to a named engineer and a named project, so faults can be traced, counted, and fed back into the error guide.
Questions after delivery are answered within 24 hours.
Ship us a sample, or just send the part number. The evaluation report tells you the scale of the die, the scope worth analysing, and the cost and schedule — and it is free of charge.