The finer the process, the higher the stake on every tape-out and the narrower the market window. CPS has completed circuit analysis on more than ten 3nm process ICs — see how it was actually done before you commit capital to a mask set.
Over eighteen years the lab, the analysis software and the operations system all became our own. Not out of principle — because nothing off the shelf fitted.
Circuit analysis quality rests on three stages: sample preparation, schematic recovery, and how the project is managed and delivered. Outsource any one of them and both speed and quality are set by someone else. Since 2008 CPS has owned all three.
Decapsulation, delayering, layer-by-layer imaging and cross-section analysis all happen in house. Samples never leave, progress never waits on a third party, and a difficult case can be re-run with different parameters the same week.
See the lab →What you receive is not image files but a probe: trace a net, cross-reference layout and schematic in both directions. Because we wrote it, a feature a customer needs is a feature we can add.
See BrigenOne →Enquiry, quotation, scope changes, delivery and support all stay on the record. You can see where the work stands, what scope was agreed, and where the files from a project three years ago are.
See CPS Portal →Together they are what makes a fast, accurate report possible at a controlled cost — and we are still pushing all three towards faster, cheaper and more advanced.
Advanced nodes magnify the cost of every decision. And a wrong one never costs just one redo.
Mask and tape-out costs at advanced nodes are not in the same league as mature ones. Pick the wrong architecture, or get a critical block wrong, and you lose a round of capital — not a few days of work.
A new product has a limited high-margin window. Another design round is rarely just another cost — it means missing the window entirely, which makes the whole effort worth very little.
A senior IC designer costs a great deal per year. If most of that time goes into debugging and trial-and-error instead of moving forward, the loss compounds every single day.
Studying a design that already works is not a shortcut — it moves engineering time from "finding what went wrong" to "deciding what to do next".
CPS reports have never been about copying. The same architecture often behaves in unexpected ways in a different product domain, and the more designs an engineer has seen, the more original their judgement becomes. That is what we want these reports to do.
From fastest to most complete. Most customers start with the first.
Chips already analysed, available immediately. The cost of the evaluation report is credited against the full version.
Search the library →Your chip, your scope. Analyse a single critical block or the whole die. Delivered as a BrigenOne project, Cadence-compatible schematics and a hierarchical PDF.
How commissioning works →You do not always need a full circuit analysis. High-resolution layer-by-layer die imaging, or device identification and net annotation on their own, are both available.
How pricing works →The two models differ in one thing only: whether the report is ever supplied to anyone else. Who is reading it is never disclosed either way.
You receive the full technical content at a third of the exclusive price. The report may later appear in our public library for other customers to buy.
Best when: you want the technology and a shorter development cycle, and do not mind the analysis being supplied to others later.
The report is never resold and stays yours alone. No second copy of this analysis exists anywhere.
Best when: beyond the technology itself, you need certainty that competitors cannot obtain the same analysis.
Whichever you choose, we never disclose who is reading a report.
This is not a paid upgrade. It is a line we have not crossed in eighteen years. Who commissioned the work, which chip they asked about, and when — we do not tell anyone.
About four in ten commissions choose Exclusive.
Search by part number, manufacturer, device type or analysis depth. Cannot find your part? We can analyse it for you.
We never disclose customer names or the existence of any commission. What follows describes only the kinds of organisation.
Over eighteen years CPS has served more than 891 customers worldwide, across North America, Europe and Asia.
We publish no customer names and confirm no engagement to anyone. That is the line this industry runs on, and it is not something price can buy. Below is only the general shape of who they are.
Including well-known specialist design houses. Used for architecture decisions, process selection, and shortening development cycles.
Used for process comparison and as measurable evidence in yield questions, taken from physical silicon.
Used to confirm how their own IP presents once taped out, and to compare it against competing implementations.
Well-known firms use circuit analysis reports as the factual technical basis underpinning their professional work.
Customers coming back for a second and third commission is the only satisfaction metric we can offer — because everything else, we are not at liberty to say.
BrigenOne is our own circuit viewer, delivered with every report. No installation — download and open.
Most of the field runs on general-purpose commercial tools. We do not.
General-purpose software was not designed for circuit analysis, and what it can do is bounded by someone else’s product roadmap. To get a new capability you wait — until the vendor decides enough people want it.
BrigenOne is ours, so the tool grows with the engineering. A viewing mode, a comparison rule, a delivery format a customer asks for is something we can assess and schedule into a release.
More importantly, owning the software is what lets us bring AI into the workflow. Recognition, comparison and first-pass assembly — the repetitive stages — run through AI first, so engineers spend their time where judgement is actually required.
Lower cost and shorter schedules end up on the quotation and the delivery date. That is what writing your own software is actually for.
From decapsulation to layer-by-layer imaging, everything happens in our own lab. Successfully processed 3nm devices, 3D NAND beyond 128 layers, and SiP packages containing 10 dies.
Netlist extraction uses a double-extraction-and-compare process, with a quality team of senior engineers reviewing every low-level block and a final review once all blocks are complete. Support questions answered within 24 hours.
New report alerts, early access to CPS School releases, online commissioning and a full record of every project — one account covers all of it, free.
The library keeps growing. Choose the device categories or manufacturers you care about — only Power Management and Driver, say — and nothing else reaches you. In this market, knowing the data exists is itself a head start.
Each public release covers a limited number of reports. Account holders get reading access ahead of the general announcement, without competing for it.
Raise a commission directly in the Portal. Enquiry, quotation, scope changes, delivery and support all stay under the same case — still findable three years later.
An account requires a company tax ID and a corporate email address; we verify against the business registry before activating it.
We periodically release part of our past circuit analysis work, free, to students, professors and anyone seriously studying semiconductor design.
The hardest thing about learning analog design is that you never get to see how others did it. Textbooks give you the principles, but the trade-offs, protection circuits and process compensation inside a shipping chip never make it into a paper.
These reports have already served their commercial purpose for us. For someone still learning, they are material that is almost impossible to find. Better that they keep working than sit on a drive.
Browse released reports →
Send us a part number, or ship us a sample. We evaluate it first so you know the cost and the schedule — and the evaluation fee is credited against the full analysis.
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