Die and process
Die size, process node, metal and poly layer counts. These directly determine wafer cost and gross die per wafer.
Competitive intelligence
You cannot read a competitor’s pricing until you understand their cost
The semiconductor market demands sustained capital, people and time. Against the risk of long development cycles, you need sharper technical, product and market intelligence to judge where a new product should go — and sometimes where the business should go.
A competitor’s selling price is public. The cost structure behind it is not — you only see that by opening the part.
The cost of an IC is not one number. It is set by die area, process node, mask layer count, package type and test time, and every one of those can be measured from physical silicon.
What we measure
Measured values, not estimates.
Package construction
Reading the package type, substrate layer count and bonding method. Advanced packaging sometimes costs more than the die itself, and magnifies yield loss.
Test cost
Assessment of CP and FT test cost — routinely overlooked, but a significant share on high pin-count parts or long test times.
Packaging is part of the same assessment
More IC products now use high-barrier bumping, multi-die packaging and SiP, while optical and heterogeneous integration packaging are common in CIS products.
For products using these advanced packages, packaging can cost more than the die, and yield problems are magnified because a failure loses the die as well.
If you need to understand substrate routing, we have extensive experience presenting the traces on every substrate layer.
Tell us which parts to compare
Send the part numbers and the cost items you care about, and we will come back with a feasible scope and schedule.
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